This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-067496, filed Mar. 12, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular, to a nonvolatile ferroelectric memory.
2. Description of the Related Art
Today, semiconductor memories are utilized in various applications, including main memories of large-scale computers as well as personal computers, electric appliances, and cellular phones. Semiconductor memories on the market include volatile DRAMs (Dynamic Random Access Memories), SRAMs (Static Random Access Memories), nonvolatile MROMs (Mask Read Only Memories), and Flash EEPROM (Flash Electrically Erasable and Programmable Read Only Memories).
In particular, the DRAM is a volatile memory but is excellent in cost (its cell area is a quarter of that of an SRAM) and speed (it operates faster than a Flash EEPROM). Thus, DRAMs now occupy the largest market share.
Further, a rewritable nonvolatile Flash EEPROM is nonvolatile and thus its power supply can be turned off. However, the number of times this Flash EEPROM can be rewritten (the number of W/Es) is only about 106. It takes microseconds to write data in the Flash EEPROM. Furthermore, a high voltage (12V to 22V) must be applied to achieve writes. The Flash EEPROM has such advantages, so that the percentage of the market taken up by the Flash EEPROM is now smaller than that taken up by the DRAM.
In contrast, since a nonvolatile ferroelectric memory employing a ferroelectric capacitor was proposed in 1980, many manufacturers have been making efforts to develop this memory. This is because it is nonvolatile, the number of times it can be rewritten is 1012, and it can operate at 3V to 5V, etc.
FIG. 1A shows a memory cell in a conventional ferroelectric memory which is composed of one transistor and one capacitor, and a cell array configuration in this memory.
In the memory cell configuration of the conventional ferroelectric memory, a transistor CT and a capacitor FC are connected together in series. The following components are arranged in the cell array: bit lines BL and/BL through which data is read, word lines WL0 and WL1 through which the memory cell transistor CT is selected, and plate lines PL0 and PL1 that drive one end of the ferroelectric capacitor FC. Furthermore, plate line driving circuits PLD0 and PLD1 are connected to the plate lines PL0 and PL1, respectively.
However, this conventional ferroelectric memory has a folded bit line configuration in which one memory cell is arranged per two intersections of the word lines and bit lines, as shown in FIG. 1B. When both interconnect width and interconnect space are defined as F, the minimum cell size is limited to 2Fxc3x974F=8F2. Thus, disadvantageously, the cell size of the conventional ferroelectric memory is limited to 8F2.
Further, in the conventional ferroelectric memory, to prevent destruction of polarization information in the ferroelectric capacitors of non-selected memory cells, the plate lines must be separated from one another so as to correspond to the respective word lines, and must be individually driven. Furthermore, a plurality of ferroelectric capacitors are connected to each plate line in the direction of the word lines. Consequently, the plate line has a large load capacity. Moreover, the pitch with which the plate line driving circuits are arranged must be similar to that with which the word lines are arranged. It is thus impossible to increase the size of each plate line driving circuit. Accordingly, it takes much time to increase or reduce the potential across the plate line. Therefore, the ferroelectric memory operates at low speed.
To solve this problem, the inventor has proposed in Jpn. Pat. Appln. KOKAI Application No. 10-255483,Jpn. Pat. Appln. KOKAI Application No. 11-177036, and Jpn. Pat. Appln. KOKAI Application No. 2000-22010, all of which have been previously filed, a new nonvolatile ferroelectric memory featuring three points that are compatible with one another: (1) small memory cells of size 4F2, (2) planar transistors that can be easily manufactured, and a (3) general-purpose fast random access function. FIG. 1C shows a configuration of the ferroelectric memory according to the previous applications.
As shown in FIG. 1C, in this ferroelectric memory, one memory cell is composed of the cell transistor CT and ferroelectric capacitor FC connected together in parallel. One memory cell block MCB is composed of a plurality of parallel-connected memory cells connected together in series. One end of the memory cell block MCB is connected to the bit line BL via a block selection transistor BST. The other end is connected to the plate line PL. Furthermore, the plate line driving circuit PLD is connected to the plate line PL. With this configuration, planar transistors can be used to realize a memory cell 101 with the minimum size of 4F2 as shown in FIG. 1D.
The ferroelectric memory shown in FIG. 1C operates as described below. A memory cell transistor and ferroelectric capacitor in a memory cell from which data is to be read are defined as CT1 and C1, respectively. Memory cell transistors and ferroelectric capacitors in other memory cells are defined as CT and FC, respectively. As shown in FIG. 2A, during standby, all word lines WL0 to WL3 are set at a xe2x80x9chighxe2x80x9d potential, and the memory cell transistors CT and CT1 are turned on. Furthermore, a signal interconnect BS0 of a block selection transistor BT0 is set at a xe2x80x9clowxe2x80x9d potential, with the block selection transistor BT0 turned off. Then, the opposite ends of each of the ferroelectric capacitors FC and C1 are electrically shorted by a corresponding one of turned-on cell transistors CT and CT1. Thus, no difference in potential occurs across each of the ferroelectric capacitors FC and C1. Storage polarization is therefore stably retained. FIG. 2B shows a hysteresis curve for the polarization capacity of the ferroelectric capacitor during standby.
Further, in operation, only the memory cell transistor connected together in parallel to a ferroelectric capacitor from which data is to be read is turned off. The other memory cell transistors are turned on. Furthermore, the block selection transistor is turned on.
For example, as shown in FIG. 2C, if the ferroelectric capacitor C1 is to be selected which belongs to the ferroelectric memory cell composed of the memory cell transistor CT1 and this ferroelectric capacitor C1, then the word line W2 is set to the xe2x80x9clowxe2x80x9d potential. Subsequently, the plate line PL is set to the xe2x80x9chighxe2x80x9d potential. The signal interconnect BS0 of the block selection transistor BT0 is set to the xe2x80x9chighxe2x80x9d potential. Then, the difference in potential between the plate line PL and the bit line BL is applied only to the opposite ends of the ferroelectric capacitor C1, connected together in parallel to the memory cell transistor CT1, which has been turned off. Polarization information on the ferroelectric capacitor C1 is read out to the bit line BL. FIG. 2D shows a hysteresis curve of polarization capacity of the ferroelectric capacitor during operation.
Thus, even if the memory cells are connected together in series, selecting an arbitrary word line enables cell information to be read from an arbitrary ferroelectric capacitor. This serves to accomplish perfect random accesses. Further, the plate line can be shared by a plurality of memory cells. The area of the plate line driving circuit can thus be increased, while reducing chip size. Therefore, high-speed operations can be realized.
However, the ferroelectric memory shown in FIG. 1C also has problems described below. As disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-177036, a ferroelectric memory of a folded bit line configuration can be actualized by providing two types of signal interconnects (gate lines) for each of two bit lines (/BL and BL) constituting a bit line pair and further providing two types of plate lines. This ferroelectric memory is shown in FIGS. 3A and 3B.
In FIG. 3A, four memory cells connected together in series (hereinafter referred to as a xe2x80x9cmemory cell blockxe2x80x9d) are arranged in each of the upper left and lower left of the circuit. The plate line PL0 is connected to the left end of upper memory cell block. The bit line/BL is connected to the right end of this memory cell block via the block selection transistor BT0, having the signal interconnect BS0 as a gate. Further, the plate line PL1 is connected to the left end of the lower memory cell block. The bit line BL is connected to the right end of this memory cell block via a block selection transistor BT1, having a signal interconnect BS1 as a gate.
For example, to select one memory cell of the upper memory cell block, only the plate line PL0 and the signal interconnect BS0 are set to the xe2x80x9chighxe2x80x9d potential, with the plate line PL1 and the signal interconnect BS1 remaining at the xe2x80x9clowxe2x80x9d potential. Cell data is thus read out only to the bit line/BL. The folded bit line configuration can then be realized by causing a sense amplifier SA to amplify the read signal using the bit line BL as a reference bit line.
In this case, because of the arrangement of the memory cell blocks, the signal interconnect BS1 must pass between the upper memory cell blocks. The signal interconnect BS0 must pass between the lower memory cell blocks. It is thus necessary to provide a bridge line BR11 composed of a metal interconnect and striding the signal interconnect BS1 and a bridge line BR12 composed of a metal interconnect and striding the signal interconnect BS0.
Further, in FIG. 3A, the memory cell blocks arranged in the upper right and lower right of the circuit have a similar configuration as shown in the figure. A contact C1 that connects the block selection transistor to the bit line is shared. A ferroelectric memory with this configuration has problems described below.
First, the bit lines have a large capacity. Even if the block selection transistor is turned off at the connection point between itself and the bit line, the capacity of two diffusion layers is connected to the bit line as shown by AA in the figure. This applies to all non-selected memory cell blocks and contributes to increasing the bit line capacity. The diffusion layers connected to the bit line include a diffusion layer AA located below the bit line contact C1 and a diffusion layer AA corresponding to the connection point between the bridge line of the metal interconnect and the block selection transistor.
Second, the block selection transistor has a large transistor area. This is because a large number of contacts are formed in the transistor area of the block selection transistor. For example, the upper two memory cell blocks require three contacts: a contact C1 connected to the bit line/BL, a contact C1 for the left memory cell block which connects the bridge line BR11 and the block selection transistor BT0 together, and a contact C1 for the right memory cell block which connects a block selection transistor BT0xe2x80x2 and the bridge line BR12 together. The contacts C1 are required for the block selection transistor. Contacts C2 are essentially required to connect a cell transistor and a cell capacitor together.
In FIG. 3B, the memory cell block is arranged in each of the upper left and lower left of circuit. The plate line PL0 is connected to the left end of the upper memory cell block. The bit line/BL is connected to the right end of this memory cell block via the block selection transistor BT0, having the signal interconnect BS0 as a gate. Further, the plate line PL1 is connected to the left end of the lower memory cell block. The bit line BL is connected to the right end of this memory cell block via the block selection transistor BT1, having the signal interconnect BS1 as a gate.
For example, to select one memory cell of the upper memory cell block, only the plate line PL0 and the signal interconnect BS0 are set to the xe2x80x9chighxe2x80x9d potential, with the plate line PL1 and the signal interconnect BS1 remaining at the xe2x80x9clowxe2x80x9d potential. Cell data is thus read out only to the bit line/BL. The folded bit line configuration can then be realized by causing the sense amplifier SA to amplify the read signal using the bit line BL as a reference bit line.
In this case, because of the arrangement of the memory cell blocks, the signal interconnect BS1 must pass between the upper memory cell blocks. The signal interconnect BS0 must pass between the lower memory cell blocks. A depression type transistor is thus used to avoid affecting the signal potential at a possible unwanted intersection of the signal interconnects BS0 and BS1.
Further, in FIG. 3B, the memory cell blocks arranged in the upper right and lower right of the circuit have a similar configuration as shown in the figure. The contact C1 that connects the block selection transistor to the bit line is shared. A ferroelectric memory with this configuration has problems described below.
First, the bit lines have a large capacity. Even if the block selection transistor is turned off at the connection point between itself and the bit line, the depression type transistor remains on. The capacity of this transistor is visible as viewed from the bit line. Furthermore, the capacity of two diffusion layers is connected to the bit line as shown by AA in the figure. This applies to all non-selected memory cell blocks and contributes to drastically increasing the bit line capacity. The diffusion layers connected to the bit line include a diffusion layer AA located below the bit line contact C1 and a diffusion layer AA corresponding to the connection point between the depression type transistor and the block selection transistor.
Second, the block selection transistor has a large transistor area. This is because it is necessary to switch, for each transistor, from ion implantation conditions required to form a channel of the depression type to those required to form a channel of an enhanced type or vice versa, thus hindering the reduction of size of the block selection transistor.
Further, if the upper left memory cell block is to be selected by setting the potential across the signal interconnect BS0 to the xe2x80x9chighxe2x80x9d value, coupling causes the potential across the bit line BL to decrease because the signal interconnect BS0 is connected to the lower depression type transistor. On the other hand, if the lower left memory cell block is to be selected by setting the potential across the signal interconnect BS1 to the xe2x80x9chighxe2x80x9d value, coupling occurs because the signal interconnect BS1 is connected to the upper depression type transistor. However, since the block selection transistor BT0, connected to the upper signal interconnect BS0, is off, the potential across the bit line/BL does not increase. Thus, signals are unbalanced between the pair of bit lines.
As described above, even the ferroelectric memory according to the previous applications, which allows the memory cell size to be reduced, has problems described below. (1) The use of a large number of contacts increases the size of the memory cell blocks. (2) An ion ejection area used to form channels is divided into small areas. This contributes to increasing the memory cell block size. (3) A large number of diffusion layers are connected to non-selected blocks. This contributes to increasing the capacity of the bit lines and reducing the magnitude of a read signal. (4) If depression type transistors are used, their channel capacity appears as a bit line capacity even in non-selected blocks. This contributes to increasing the bit line capacity and reducing the magnitude of a read signal. (5) If depression type transistors are used, signals are unbalanced between the pair of bit lines.
According to an aspect of the present invention, there is provided a semiconductor storage device comprising a first memory cell block having a plurality of memory cells connected together in series, each of the memory cells comprising a cell transistor and a ferroelectric capacitor, the ferroelectric capacitor having an electrode at one end and an electrode at the other end which are connected to a source and a drain of the cell transistor, respectively; a first block selection transistor which selects the first memory cell block; a first metal interconnect connected between one end of the first memory cell block and one end of a current path in the first block selection transistor; a first bit line connected to the other end of the current path in the first block selection transistor; a second bit line arranged adjacent to the first bit line; and second and third block selection transistors each having a current path one end of which is connected to the second bit line, wherein interconnects connected to gate electrodes of the second and third block selection transistors are disposed below the first metal interconnect.